meeting date: 03 jan 2006
attending: Todd Westerhoff, Bob Ross, Ian Dodd, Mike LaBonte, Arpad Muranyi,
           Ken Willis

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Review of ARs:

Ian try to add examples to BIRD
- TBD

Paul choose a parser platform
- Paul is not currently active

Mike finish documentation examples.
- TBD

Todd get response from Xilinx
- TBD

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Arpad's progress
- VHDL-AMS nearly finished
- hoping to get as close as possible to Verilog-A version
- efficiency improvements have since been made in Verilog-A version
- will be repeated in VHDL-AMS version

HSPICE fix
- Arpad tried the fixes
- they work one at a time, but not together

Where are we headed?
- Need well-packaged downloadable kit
- Need 3 IC vendors to ship IBIS files
- Need at least 1 EDA vendor supporting the library
  - likely:
    - Verilog-A: Cadence, Synopsys
    - VHDL-AMS: Mentor
    - SPICE: SiSoft?
- EDA vendors supporting both?
  - depends on customer demand
  - Verilog-A sold for Mentor IC design

DesignCon:
- Feb 9, IBIS meeting is Thursday
- Presentation 1: Give status update
  - Todd will present.
  - Report that we are actively recruiting.
  - report that NCSU is on board.
- Presentation 2: Explain how each element works
  - Arpad will present.
- Cleanup website, make a downloadable kit
  - Mike should have admin permission.
  - Testcases in for at least, because everyone has it.
  - Make room for testcases targeting any/all simulator.

AR: Mike cleanup website
AR: Arpad propose IBIS summit presentation
AR: Todd propose IBIS summit presentation

Ongoing ARs:

AR: Ian try to add examples to BIRD
AR: Paul choose a parser platform
AR: Mike finish documentation examples.
AR: Todd get response from Xilinx

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Next meeting: Tuesday 10 jan 2006